Tag: RISC-V
From zoned storage to root-of-trust chips to shared memory pools, we're leading open-source innovation to drive new system architectures. Learn more…
February 24, 2020
By Richard New
The first RISC-V Hackathon in Israel included students from Bar-Ilan and Ben-Gurion Universities, developers from NextSilicon and GSOC solutions, and…
February 4, 2020
By Amir Fridman
Our open sourced RISC-V-based SweRV Core family is growing by two as we announce the world’s first commercial dual-threaded embedded core, SweRV…
December 10, 2019
The 2019 RISC-V Summit, December 10-12 in San Jose, is a can’t-miss event for everyone interested in learning how the free and open ISA is…
November 18, 2019
OmniXtend is the open approach to providing cache coherent memory over an Ethernet fabric & can enable innovation in next-generation data-centric…
June 18, 2019
We delivered on our promise to open source the SweRV Core, which supports our internal RISC-V development efforts & those of the growing RISC-V…
April 11, 2019
At the first RISC-V Summit in Santa Clara, California, Western Digital EVP & CTO Martin Fink delivered a keynote entitled, "Unleashing Innovation…
December 19, 2018
The RISC-V Summit in Santa Clara, California, is a can’t-miss event for everyone interested in learning how the free and open ISA is transforming…
November 27, 2018
This morning we launched a fully redesigned westerndigital.com—and it’s more than a visual makeover. This new site truly reflects who ...
November 12, 2018
By Mike Cordano
Learn about accelerating the RISC-V ecosystem: 1. The current state of the ecosystem; 2. What it needs and the work that must be done. For those who…
October 1, 2018