Whether you’re a veteran RISC-V enthusiast or brand new to the world of open-source instruction set architecture (ISA), the RISC-V Summit next week in Santa Clara, California, is a can’t-miss event for everyone interested in learning how the free and open ISA is transforming the computing landscape and beyond.
Here are the key reasons not to miss the summit!
- Keynote presentations with new product reveals – RISC-V Foundation member companies tend to make major announcements at events, like the Western Digital core plan. Be among the first to hear what’s new by attending featured keynotes from Western Digital, Qualcomm, NXP, Microchip, and more.
- With major media organizations, reporters and editors in attendance at the Summit, you’ll have a chance to talk with them about RISC-V and share your applications and ideas. They’re coming to Santa Clara to gauge the pulse of this community and to find what the ecosystem is so excited about!
- Lots of new announcements from 30+ exhibitor booths on the floor of the Main Expo. You’ll be able to get your hands on the latest products and solutions emerging in the RISC-V ecosystem from leading companies as Western Digital, Microsemi, SiFive, NXP, Qualcomm, Antmicro and many more!
- The open collaboration and amazing discussions to be had with RISC-V members. We’re expecting over 1,000 attendees. You’ll talk with people from around the globe about your applications and ideas, and learn how RISC-V can mesh with your use cases and goals.
- THE PARTIES! Enjoy both the welcoming party on Monday and the Innovation Celebration on Tuesday. Network with your peers and industry leaders.
Join us for the inaugural RISC-V Summit (December 3 – 6, 2018, at the Santa Clara Convention Center).
You’ll experience three days (December 3 – 5) of tutorials, presentation and keynotes on the software ecosystem, open platforms, and accelerators for RISC-V, along with a fourth day (December 6) of RISC-V Foundation member meetings and updates. View the agenda here.
