Western Digital has delivered on our promise to open source the SweRV CoreTM.
First announced at the RISC-V Summit, the SweRV core is one of three open-source innovations designed to support Western Digital’s internal RISC-V development efforts and those of the growing RISC-V ecosystem. The Western Digital SweRV Core EH1 is the first production grade, open source RISC-V core and we, Western Digital, did it!
Western Digital is pleased to provide the SweRV Core to the open source community. The initial response and targeted uses are gratifying to the entire development team and all of Western Digital. We look forward to the acceleration of the RISC-V ecosystem and the innovations which will result from this core. –Martin Fink, CTO Western Digital
The SweRV Core EH1 is a 32-bit, 2-way superscalar, 9 stage pipeline core. With an expected performance of up to 5.0 CoreMarks/MHz (based on internal simulations) and small footprint, it offers compelling capabilities for embedded devices supporting data-intensive edge applications, such as storage controllers, industrial IoT, real-time analytics in surveillance systems, and other smart systems. The power-efficient design also offers clock speeds of up to 1.8Ghz on a 28nm CMOS process technology.
The SweRV Core will be used in Western Digital products in the coming years. The SweRV Core EH1 is now open sourced for the RISC-V community to utilize and contribute to. It is available on GitHub at https://github.com/westerndigitalcorporation/swerv_eh1.
Good Response and FPGA Implementation
Since the posting of the SweRV Core, there have been thousands of visitors and the core has been cloned many hundreds of times.
Following the initial posting, Western Digital was asked to target a Field Programmable Gate Array (FPGA) so that many others could develop, modify and contribute to the SweRV Core. The team has responded and there is now a FPGA implementation of SweRV on GitHub. See all the details at https://github.com/westerndigitalcorporation/swerv_eh1_fpga.
The release of this production grade RISC-V core will accelerate the RISC-V ecosystem development and the overall usage of RISC-V in the commercial market.
Ensuring Cores Execute Instructions Properly
To go along with the SweRV Core, Western Digital has also open sourced the SweRV ISS™ (Instruction Set Simulator). This was developed independently from the SweRV Core to ensure RISC-V cores are executing instructions properly. The SweRV ISS is also available for download with full test bench support for validation of RISC-V cores.
The SweRV ISS models closely coupled memories, caches, interrupts and more. It was used to rigorously simulate and validate the SweRV Core, with more than 10 billion instructions executed. Download it at https://github.com/westerndigitalcorporation/swerv-iss.
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Also, check out CPU Project in Western Digital: From Embedded Cores for Flash Controllers to Vision of Datacenter Processors with Open Interfaces, a presentation by Western Digital at the recent RISC-V Summit:
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