Storage Class Memory (SCM), with its high endurance, expanded capacity and low latency has the potential to transform the management of “Big Data” in the near future. At Western Digital, we continue our commitment to SCM through the ongoing exploration of innovative new ways to support customers and ecosystem partners in the adoption of this ground-breaking technology.
A New Prototype Memory Controller
At the super computing conference SC16 in Utah this week, Western Digital’s San Jose Research Center will showcase its latest innovation in SCM: a prototype memory controller created from the ground up to enable the efficient deployment of SCM as main memory in a wide variety of scenarios including those with heterogeneous compute engines and accelerators.
To realize its full potential, SCM requires a new kind of memory controller which appears as a DRAM controller to caches and processors while seamlessly incorporating complex media management on the memory side. To ease adoption it must work well with today’s most common legacy peripheral attach points.
The new Western Digital SCM prototype being shown at SC16 utilizes RapidIO, an open, widely deployed interconnect used for performance critical computing. It enables coherent communication with caches on a variety of compute engines, including ARM, RISC-V (an open source architecture), field-programmable gate arrays (FPGA), digital signal processors (DSP), and others. This architecture can seamlessly incorporate non-coherent peripherals, including x86 through a PCI Express bridge. Additionally, the prototype has the ability to leverage SCM as the main memory, without having to keep another working copy in DRAM for execution.
Incorporating SCM into the Memory Hierarchy
This new approach to incorporating SCM into the memory hierarchy can potentially provide the flexibility to deploy ultra-low latency, coherent SCM across high-performance computing and hyperscale environments, without disrupting compatibility with the existing infrastructure, scaling up to petabytes of data generated by applications and analytics in the age of “Big Data”.
Attendees of the SC16 Conference can discuss the demo with the researchers in the RapidIO.org booth #731 this week. We look forward to seeing you there.
Dejan Vučinić, is Director, R&D Engineering, Non-Volatile Memory Systems Architecture Group at Western Digital.