On the microscopic level, we’re using 3D NAND technology to build “skyscrapers” that house data. And there’s more to it than just adding more floors – or scaling vertically. We’ve had to innovate to meet growing data demands driven by artificial intelligence, connected cars, IoT, mobile, and other uses. That’s meant finding smarter ways to pack more bits into tighter spaces, without sacrificing cost or too much performance.

In this blog post, I’ll cover how our approach to scaling – vertically, laterally, and logically – has led to incredible gains in efficient data storage. I explore these ideas further in my recent presentation at Storage Field 19, which you can watch below.

A “Skyscraper” Analogy for 3D NAND

Let’s take a closer look at the analogy of skyscrapers to visualize the concept of 3D NAND. Similar to a building with floors, 3D NAND uses layers of semiconducting material stacked on a wafer. Each layer is filled with “rooms”, or memory cells. Memory cells can be programmed to store one or more bits – similar to the occupancy for a room in a skyscraper. Finding this balance between bit density, read and write speeds, and cost is where the data storage battle is won.

Vertical Scaling – Building Up Our 3D NAND Tower

You might have seen our recent announcement introducing BiCS5, our fifth-generation and highest density 3D NAND technology. At 112 layers, it continues to raise the bar from its 96-layer predecessor – with capacity and performance bumps to boot. This follows our previous innovation with 64-layer and 48-layer flash memory, in 2017 and 2016, respectively.

But, the process gets complicated as we add more layers to our data structure. There are additional capital expenditures to consider. Simply put, as the number of NAND layers rises, it becomes increasingly costly to add more storage capacity. We’ve seen this trend consistently during our transition from 2D to 3D NAND. Think of it as being more expensive to build out the 100th floor of a skyscraper than the 10th floor. It would be cost intensive to move construction equipment, supplies, and workers into higher and potentially more dangerous locations.

Lateral Scaling – Fitting More Memory Cells on Each Layer

Like I mentioned before, smart scaling is more than a “who-can-build-it-higher” contest. It takes innovation in storage density to efficiently move data at scale. To go back to our analogy, this means finding ways to add more rooms on each floor of our 3D NAND skyscraper. At the silicon wafer-level, this means making sure that the memory cells are as close and narrow as possible.

One big factor in density is the size of memory holes. These are holes in the 3D NAND structure around which we build and stack cells. Narrower memory holes free up space on the wafer to place additional memory cells. Our innovation in multi-tiered memory holes is helping bring this reality to life. In this technique, we drill a memory hole in two shots instead of one, to squeeze more bits onto a wafer. It’s similar to building out half of a floor in a skyscraper, moving the construction equipment and supplies up, and then starting construction on the next floor.

We also want to reduce overhead – all of the “non-room” space in the 3D NAND skyscraper. This overhead comes from the physical infrastructure necessary to communicate with each memory cell, particularly the alternating film deposition that makes up the 3D NAND stack. Thanks to our advancements in flash memory production, we’ve been able to free up space on each layer to efficiently scale data storage.

Logical Scaling – Finding More Room for Data Bits

The final piece of the smart scaling puzzle is logical scaling. Returning to our analogy, this is similar to the maximum occupancy per room on each level of a skyscraper. In 3D NAND, logical scaling is the process of storing more bits in each memory cell.

When it comes to bit density, however, there is a tradeoff between capacity and performance. It’s true that more bits stored per cell increases the amount of data that can be stored. A byproduct, though, is that writing to a memory cell takes longer because existing data in the cell must be transferred and the cell overwritten. Also, reading from a memory cell takes longer due to longer access times to read a particular location in the cell.

The law of diminishing returns also comes into effect for scaling. Consider the following scenario. When we go from 1 bit per memory cell (SLC) to 2 bits (MLC), storage capacity doubles – a 100 percent scaling benefit. However, as we fit more bits into each cell, this benefit decreases. We’re currently migrating from 3 bits per cell (TLC) to 4 bits per cell (QLC), which has a 33 percent scaling benefit. At some point, we need optimization at the system and workload level make up the difference.

Thanks to our strong investment in vertical integration, we’re able to do so. We design end-to-end flash memory solutions, from memory cells to components to firmware to devices to platforms. This enables us to fine tune our 3D NAND design parameters. We can balance storage density with demands in cost, power, reliability, and speed. 

Our Continued Commitment to 3D NAND Technology

To keep up with exponential data growth in the Zettabyte Age, companies increasingly must scale to survive. It’s a challenge that we’ve addressed by scaling with 3D NAND – vertically, laterally, and logically. Now, we’ve reached 112-layer flash memory structures that work intelligently to store more data than ever. All the while, technical innovation is helping keep costs low. We’ll continue to innovate in 3D NAND technology to better move data where and when it needs to go, raising value for the people that depend on it the most.

See 3D NAND in Action

 

 

Luca Fasoli, Ph.D., is Vice President, Memory Product Solutions for Western Digital.